Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. The TL16CB offers enhanced features. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements.
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On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics. Characters can be programmed to be 5, 6, 7, or 8 bits.
The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. Internal registers address selection Address 1 select bit. Internal registers address selection Address 2 select bit. Internal registers address selection Carrier detect active low.
A low on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register MSR. Chip select A and B active low. Clear to send active low. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register EFR bit 7, for hardware flow control operation. These pins are the eight bit, 3-state data bus for transferring information to or from the controlling CPU.
D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Data set ready active low. A logic low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register MSR Data terminal ready active low.
These pins can be controlled through the modem control register. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset.
Signal and power ground Interrupt A and B active high. Interrupt conditions include: receiver errors, available receiver buffer data, available transmit buffer space or when a modem status flag is detected. INTA—B are in the high-impedance state after reset. Read input active low strobe.
Write input active low strobe. This function is associated with individual channels A and B. The state of these pins is defined by the user through the software settings of the MCR register, bit 3. See bit 3, modem control register MCR bit 3. The output of these two pins is high after reset. RESET resets the internal registers and all the outputs.
The UART transmitter output and the receiver input is disabled during reset time. RESET is an active-high input. Ring indicator active low.
A logic low on these pins indicates the modem has received a ringing signal from the telephone line. A low to high transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the modem status register MSR Request to send active low.
A low on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the modem control register MCR bit 1 sets these pins to low, indicating data is available. After a reset, these pins are set to high.
These pins only affect the transmit and receive operation when auto RTS function is enabled through the enhanced feature register EFR bit 6, for hardware flow control operation.
Receive data input. Receive ready active low. Transmit data. Transmit ready active low. They go high when the TX buffer is full. Power supply inputs. Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. Alternatively, an external clock can be connected to XTAL1 to provide custom data rates. Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator output or buffered a clock output.
It takes three samples of the RX line and uses a majority vote to determine the logic level received. The vote logic operates on all bits received. It provides more enhanced features. All additional features are provided through a special enhanced feature register.
The UART performs a serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. Both the receiver and transmitter FIFOs can store up to 64 bytes including three additional bits of error status per byte for the receiver FIFO and have selectable or programmable trigger levels. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals.
The UART includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and —1. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR. The programmable trigger levels are available via the TLR. Thus, overrun errors are eliminated during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency.
Figure 1 shows RTS functional timing. The sending device e. This reassertion allows the sending device to resume transmission. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS.
Figure 1. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte. CTS must be deasserted before the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host system. When flow control is enabled, the CTS state changes and need not trigger host interrupts because the device automatically controls its own transmitter.
Figure 2 shows CTS functional timing, and Figure 3 shows an example of autoflow control. When CTS is low, the transmitter keeps sending serial data out B. When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does not send the next byte. When CTS goes from high to low, the transmitter begins sending data again.
Figure 2. Different combinations of software flow control can be enabled by setting different combinations of EFR[3—0]. Table 1 shows software flow control options. Detection of the special character sets the Xoff interrupt [IIR 4 ] but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. Table 1. When the correct Xoff characters are received, transmission is halted after completing transmission of the current character.
An important note here is that if, after an xoff character has been sent and software flow control is disabled, the UART transmits Xon characters automatically to enable normal transmission to proceed. Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs.
It is assumed that software flow control and hardware flow control are never enabled simultaneously.